In semiconductor technology, interconnect arrangements are used to form wiring for semiconductor components. In this case, a dielectric layer or insulating layer is normally formed on an electrically conductive mount substrate, such as a semiconductor substrate, and an electrically conductive interconnect layer is formed on this dielectric layer, with the interconnect layer representing the final interconnect, after structuring. Further insulating layers and electrically conductive layers are then formed successively, thus resulting in a layer stack which allows even complex wiring structures.
The electrical characteristics of the interconnect arrangement in this case depend primarily on the materials used and in particular on the electrical conductivity of the interconnects, as well on parasitic capacitances per area section or length section of the interconnect.
Particularly in semiconductor memory cells such as DRAM memory cells, stored information is transported via a bit line to an evaluation circuit. FIG. 12 shows a simplified equivalent circuit of a conventional DRAM memory cell in which a storage capacitor CS is connected via a selection transistor AT to a bit line BL. The storage capacitor CS can be a trench capacitor or an MIM (metal-insulator-metal) capacitor. The selection transistor AT can be actuated via a word line WL such that the charge or information stored in the storage capacitor CS can be read via the bit line BL. The electrical characteristics of the bit line are determined primarily by their length l and the conductivity per unit length, and the parasitic capacitance CP per unit length and/or unit area. As shown in FIG. 12, the parasitic capacitance CP is charged and discharged with the charge stored in the storage capacitor CS of the memory cell. To attenuate the original signal as little as possible, the parasitic capacitance of the bit line as well as a parasitic line resistance (which is not illustrated) is minimized. To achieve this minimization, the length of the bit lines is optimized.
U.S. Pat. No. 5,461,003 filed on May 27, 1994 and issued on Oct. 24, 1995 discloses an interconnect arrangement in which air gaps or non-conductive gases or a vacuum are/is used to reduce the capacitive coupling between adjacent interconnects. In this case, a porous dielectric covering layer was used for the removal of a sacrificial layer used for the air gap, while at the same time ensuring sufficient mechanical robustness. However, further improvements in the electrical characteristics are obtained.
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